------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          user_logic.vhd
-- Version:           1.00.b
-- Description:       User logic.
-- Date:              Wed Dec 14 13:57:18 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;

-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_SLV_DWIDTH                 -- Slave interface data bus width
--   C_NUM_REG                    -- Number of software accessible registers
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Reset                 -- Bus to IP reset
--   Bus2IP_Data                  -- Bus to IP data bus
--   Bus2IP_BE                    -- Bus to IP byte enables
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
--   IP2Bus_Data                  -- IP to Bus data bus
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
--   IP2Bus_Error                 -- IP to Bus error response
------------------------------------------------------------------------------

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_SLV_DWIDTH                   : integer              := 32;
    C_NUM_REG                      : integer              := 4
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
	 hsynch,vsynch,red,green,blue : out STD_LOGIC;
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
    IP2Bus_RdAck                   : out std_logic;
    IP2Bus_WrAck                   : out std_logic;
    IP2Bus_Error                   : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

  attribute SIGIS : string;
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic
  	 signal x_ball,y_ball : std_logic_vector(9 downto 0);
	 signal y_raqG,y_raqD,score,mur1,mur2 : std_logic_vector(7 downto 0);

  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg1                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg2                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg3                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg_write_sel              : std_logic_vector(0 to 3);
  signal slv_reg_read_sel               : std_logic_vector(0 to 3);
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;
  
COMPONENT VGAtop IS
  PORT (clk_50 : in STD_LOGIC; -- horloge 50MHz
-- coordonnées de la balle
     x_rect, y_rect: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-- oordonnées des deux raquettes
     y_raquG, y_raquD: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- valeurs à afficher sur les scores : 8 bits sur deux digits
     scoreG : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- lignes de briques verticales (deux seulement)
     ligne1,ligne2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- en sortie nos cinq signaux VGA
     hsynch,vsynch,red,green,blue : out STD_LOGIC);
END component;

begin

  --USER logic implementation added here

  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  -- 
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic,
  -- you are basically operating on the following memory mapped registers:
  -- 
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  --                     "1000"   C_BASEADDR + 0x0
  --                     "0100"   C_BASEADDR + 0x4
  --                     "0010"   C_BASEADDR + 0x8
  --                     "0001"   C_BASEADDR + 0xC
  -- 
  ------------------------------------------
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 3);
  slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
  slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);

  -- implement slave model software accessible register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
        slv_reg1 <= (others => '0');
        slv_reg2 <= (others => '0');
        slv_reg3 <= (others => '0');
      else
        case slv_reg_write_sel is
          when "1000" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0100" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0010" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when "0001" =>
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model software accessible register(s) read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
  begin

    case slv_reg_read_sel is
      when "1000" => slv_ip2bus_data <= slv_reg0;
      when "0100" => slv_ip2bus_data <= slv_reg1;
      when "0010" => slv_ip2bus_data <= slv_reg2;
      when "0001" => slv_ip2bus_data <= slv_reg3;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
                  (others => '0');

  IP2Bus_WrAck <= slv_write_ack;
  IP2Bus_RdAck <= slv_read_ack;
  IP2Bus_Error <= '0';
  ------------------------------------------
  -- my own signals  
  ------------------------------------------
  x_ball <= slv_reg0(22 to 31);
  y_ball <= slv_reg0(6 to 15);
  y_raqG <= slv_reg1(24 to 31);
  y_raqD <= slv_reg1(8 to 15);
  score <= slv_reg2(24 to 31);
  mur1 <= slv_reg3(24 to 31);
  mur2 <= slv_reg3(8 to 15);
  ------------------------------------------
  -- my own components  
  ------------------------------------------
   USER_LOGIC_II : VGAtop
    port map (
	   clk_50    =>  Bus2IP_Clk,
		x_rect    =>  x_ball,
		y_rect    =>  y_ball,
		y_raquG   =>  y_raqG,
		y_raquD   =>  y_raqD,
		scoreG    =>  score,
		ligne1    =>  mur1,
		ligne2    =>  mur2,
		hsynch    =>  hsynch,
		vsynch    =>  vsynch,
		red       =>  red,
		green     =>  green,
		blue      =>  blue
	 );
	 
end IMP;

library IEEE;
use  IEEE.STD_LOGIC_1164.all;
-- 22th November 2011
-- Casse-briques avec deux lignes asymétriques
--entité VGA globale
ENTITY VGAtop IS
  PORT (clk_50 : in STD_LOGIC; -- horloge 50MHz
-- coordonnées de la balle
     x_rect, y_rect: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-- oordonnées des deux raquettes
     y_raquG, y_raquD: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- valeurs à afficher sur les scores : 8 bits sur deux digits
     scoreG : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- lignes de briques verticales (deux seulement)
     ligne1,ligne2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- en sortie nos cinq signaux VGA
     hsynch,vsynch,red,green,blue : out STD_LOGIC);
END VGAtop;
ARCHITECTURE atop of VGAtop is
  COMPONENT VGA_SYNC IS -- ***** composant présenté en exercice 1 **********
    PORT(clock_25Mhz : IN STD_LOGIC;
-- c’est ce composant qui gère les signaux de synchronisation
      horiz_sync_out, vert_sync_out : OUT STD_LOGIC;
-- et qui sait où est le point dessiné sur l'écran
      pixel_row, pixel_column: OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
  END COMPONENT;
  COMPONENT rect IS PORT( --ancien rectangle avant les generic
    row,col,x_rec,y_rec,delta_x,delta_y :in STD_LOGIC_VECTOR(9 DOWNTO 0);
    colorRGB : in  STD_LOGIC_VECTOR(2 DOWNTO 0);
    red1,green1,blue1 : out std_logic);
  END component; 
  COMPONENT aff7seg IS --un afficheur complet 7 segments
    generic (gx, gy, gdx, gdy : natural);
    port(e_7seg : in std_logic_vector(3 downto 0);
      segx, segy : in std_logic_vector(9 downto 0);
      Sseg_red, Sseg_green, Sseg_blue : out std_logic);
  END COMPONENT;
  COMPONENT ligne8briques is
        generic (gx, gy, gdx, gdy : natural); --gx, gy = position ; gdx, gdy = tailles
        port(e_8 : in std_logic_vector(7 downto 0); -- valeur à affichier
          segx, segy : in std_logic_vector(9 downto 0);-- où en est le balayage de l'écran ?
          Sseg_red, Sseg_green, Sseg_blue : out std_logic); -- signaux de couleurs
  END COMPONENT;
  
  signal clk_25,sred,sgreen,sgreen3,sblue3,sblue5,sred5,sgreen5,sred6,sblue6,sgreen6,sred7,sblue7,sgreen7,
    sred3,sblue,sred1,sgreen1,sblue1,sred2,sgreen2,sblue2,sblue4,sgreen4,sred4 : std_logic;
  signal srow,scol : STD_LOGIC_VECTOR(9 DOWNTO 0);
--signal s_aff1,s_aff2 : std_logic_vector(7 downto 0);
begin -- comme VGA_SYNC nécessite 25MHz, on divise nos 50MHz par deux
  process(clk_50) begin
    if clk_50'event and clk_50='1' then
           clk_25 <= not clk_25; --clk_25 est à 25MHz comme son nom l'indique...
         end if;
  end process;        
  i1:vga_sync port map(clock_25Mhz =>clk_25,horiz_sync_out=>hsynch,vert_sync_out=>vsynch,
                                        pixel_row=>srow,pixel_column=>scol);
  balle:rect port map(row=>srow,col=>scol,red1=>sred,green1=>sgreen,blue1=>sblue,colorRGB=>"111",
                        delta_x=>"0000001010",delta_y=>"0000001100",
                        x_rec => x_rect, y_rec => y_rect);
  bord:rect port map(row=>srow,col=>scol,red1=>sred3,green1=>sgreen3,blue1=>sblue3,colorRGB=>"111",
                        delta_x=>"1010000000",delta_y=>"0000001000",
                        x_rec => "0000000000", y_rec => "0110100110");
--  bord_score:rect port map(row=>srow,col=>scol,red1=>sred8,green1=>sgreen8,blue1=>sblue8,colorRGB=>"001",
--                        delta_x=>"0000010100",delta_y=>"0000000110",
--                        x_rec => "0100101110", y_rec => "0111000000");                                      
  raquetteG:rect port map(row=>srow,col=>scol,red1=>sred1,green1=>sgreen1,blue1=>sblue1,colorRGB=>"100",
                        delta_x=>"0000001010",delta_y=>"0000111010",
                        x_rec => "0000010110", y_rec(8 downto 1) => y_raquG, y_rec(9)=>'0',y_rec(0)=>'0');        
  raquetteD:rect port map(row=>srow,col=>scol,red1=>sred2,green1=>sgreen2,blue1=>sblue2,colorRGB=>"100",
                        delta_x=>"0000001010",delta_y=>"0000111010",
                        x_rec => "1001001000", y_rec(8 downto 1) => y_raquD,y_rec(9)=>'0',y_rec(0)=>'0');   
  affich0:aff7seg generic map(gx=>140,gy=>435,gdx=>40,gdy=>40)
        port map(e_7seg=>scoreG(7 downto 4), segx=>scol,segy=>srow,Sseg_red=>sred4,
               Sseg_blue=>sblue4,Sseg_green=>sgreen4);
  affich1:aff7seg generic map(gx=>190,gy=>435,gdx=>40,gdy=>40)
        port map(e_7seg=>scoreG(3 downto 0),segx=>scol,segy=>srow,Sseg_red=>sred5,
               Sseg_blue=>sblue5,Sseg_green=>sgreen5);
  line1:ligne8briques generic map(gx=>420,gy=>0,gdx=>20,gdy=>422)
        port map(e_8=>ligne1,segx=>scol,segy=>srow,Sseg_red=>sred6,
               Sseg_blue=>sblue6,Sseg_green=>sgreen6);              
  line2:ligne8briques generic map(gx=>440,gy=>0,gdx=>20,gdy=>422)
        port map(e_8=>ligne2,segx=>scol,segy=>srow,Sseg_red=>sred7,
               Sseg_blue=>sblue7,Sseg_green=>sgreen7);  
 
  red <= sred or sred1 or sred2 or sred3 or sred4 or sred5 or sred6 or sred7;
  green <= sgreen or sgreen1 or sgreen2 or sgreen3 or sgreen4 or sgreen5 or sgreen6 or sgreen7;
  blue <= sblue or sblue1 or sblue2 or sblue3 or sblue4 or sblue5 or sblue6 or sblue7;  
end atop;
 
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;
--use ieee.numeric_std.all;
 
ENTITY rect IS PORT( --ancien rectangle
  row,col,x_rec,y_rec,delta_x,delta_y :in STD_LOGIC_VECTOR(9 DOWNTO 0);
  colorRGB : in  STD_LOGIC_VECTOR(2 DOWNTO 0);
  red1,green1,blue1 : out std_logic);
END rect; 
ARCHITECTURE arect of rect is begin
  PROCESS(row,col,x_rec,y_rec) BEGIN
    if row > y_rec and row < y_rec+delta_y then
      if col >x_rec and col < x_rec+delta_x then
             red1 <= colorRGB(2);
                  green1 <= colorRGB(1);
                  blue1 <= colorRGB(0);
                 else  
                   red1 <= '0';
                   green1 <= '0';
                   blue1 <= '0';
            end if;
          else  
                   red1 <= '0';
                   green1 <= '0';
                   blue1 <= '0';   
          end if;  
        end process;  
end arect;                    
----------------------------------------------------------------------------------
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;
-- nouveau rectangle avec les generic
ENTITY rect_generic is 
        generic(x,y,dx,dy : natural);
        port(vgax, vgay : in std_logic_vector(9 downto 0);
                  RGB : in std_logic_vector(2 downto 0);
                  e_rect : in std_logic;
                  s_red, s_blue, s_green : out std_logic);
END rect_generic;
 
ARCHITECTURE arect_gen OF rect_generic IS
  BEGIN
        PROCESS (vgax, vgay, e_rect) 
                BEGIN
                        IF vgax>x AND vgax<x+dx THEN
                                IF vgay>y and vgay<y+dy THEN
                                        IF e_rect = '1' THEN
                                                s_red   <= RGB(0);
                                                s_green <= RGB(1);
                                                s_blue  <= RGB(2);
                                        ELSE
                                                s_red   <= '0';
                                                s_green <= '0';
                                                s_blue  <= '0';
                                        END IF;
                                ELSE
                                        s_red   <= '0';
                                        s_green <= '0';
                                        s_blue  <= '0';
                                END IF;
                        ELSE
                                s_red   <= '0';
                                s_green <= '0';
                                s_blue  <= '0';
                        END IF;
        END PROCESS;
END arect_gen; 
 
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;
-- transcodeur BCD/7 segments 
-- ATTENTION à l’ordre étrange des segments, mais ceci est transparent...
entity trans is
    port (
        e_trans: in STD_LOGIC_VECTOR (3 downto 0);     -- binary input nybble to be decoded
        s_trans: out STD_LOGIC_VECTOR (6 downto 0)      -- decoded nybble connected the seven segment display
    );
end trans;
 
architecture seg7_trans of trans is
begin
        process (e_trans)
        begin
                CASE e_trans is      -- segments : dcegbfa
                        when "0000" => s_trans <= "1110111";
                        when "0001" => s_trans <= "0100100";
                        when "0010" => s_trans <= "1011101";
                        when "0011" => s_trans <= "1101101";
                        when "0100" => s_trans <= "0101110";
                        when "0101" => s_trans <= "1101011";
                        when "0110" => s_trans <= "1111011";
                        when "0111" => s_trans <= "0100101";
                        when "1000" => s_trans <= "1111111";
                        when "1001" => s_trans <= "1101111";
                        when others => s_trans <= "0000000";
                end CASE;
        end process;                                                 
end seg7_trans;               
 
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;
-- afficheur complet sept segments
entity aff7seg is
        generic (gx, gy, gdx, gdy : natural); --gx, gy = position ; gdx, gdy = tailles
        port(e_7seg : in std_logic_vector(3 downto 0); -- valeur à affichier
          segx, segy : in std_logic_vector(9 downto 0);-- où en est le balayage de l'écran ?
          Sseg_red, Sseg_green, Sseg_blue : out std_logic); -- signaux de couleurs
end aff7seg;
 
architecture a_aff of aff7seg is
        component rect_generic
                generic(x,y,dx,dy : natural);
                port(vgax, vgay : in std_logic_vector(9 downto 0);
                  RGB : in std_logic_vector(2 downto 0);
                  e_rect : in std_logic;
                  s_red, s_blue, s_green : out std_logic);
        end component;
 
        component trans
                port(e_trans : in std_logic_vector(3 downto 0);
                          s_trans : out std_logic_vector(6 downto 0));
        end component;
 
        signal sig_aff_red, sig_aff_green, sig_aff_blue, seg_trans : std_logic_vector(6 downto 0);
 
        begin
                i1 : rect_generic generic map (x=>gx+(10*gdx)/55, y=> gy, dx =>(35*gdx)/55, dy=>gdy/10)
                  port map (RGB=>"100", e_rect=>seg_trans(0), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(0), s_green=>sig_aff_green(0), s_blue=>sig_aff_blue(0));
 
                i2 : rect_generic generic map (x=>gx, y=> gy+(gdy/10), dx =>(10*gdx)/55, dy=>(35*gdy)/100)
                  port map (RGB=>"100", e_rect=>seg_trans(1), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(1), s_green=>sig_aff_green(1), s_blue=>sig_aff_blue(1));
 
                i3 : rect_generic generic map (x=>gx+(9*gdx)/11, y=> gy+(gdy/10), dx =>(10*gdx)/55, dy=>(35*gdy)/100)
                  port map (RGB=>"100", e_rect=>seg_trans(2), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(2), s_green=>sig_aff_green(2), s_blue=>sig_aff_blue(2));
 
                i4 : rect_generic generic map (x=>gx+(10*gdx)/55, y=> gy+(gdy*9)/20, dx =>(35*gdx)/55, dy=>gdy/10)
                  port map (RGB=>"100", e_rect=>seg_trans(3), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(3), s_green=>sig_aff_green(3), s_blue=>sig_aff_blue(3));
 
                i5 : rect_generic generic map (x=>gx, y=> gy+(gdy*55)/100, dx =>(10*gdx)/55, dy=>(35*gdy)/100)
                  port map (RGB=>"100", e_rect=>seg_trans(4), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(4), s_green=>sig_aff_green(4), s_blue=>sig_aff_blue(4));
 
                i6 : rect_generic generic map (x=>gx+(9*gdx)/11, y=> gy+(55*gdy)/100, dx =>(10*gdx)/55, dy=>(35*gdy)/100)
                  port map (RGB=>"100", e_rect=>seg_trans(5), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(5), s_green=>sig_aff_green(5), s_blue=>sig_aff_blue(5));
 
                i7 : rect_generic generic map (x=>gx+(10*gdx)/55, y=> gy+(gdy*9)/10, dx =>(35*gdx)/55, dy=>gdy/10)
                  port map (RGB=>"100", e_rect=>seg_trans(6), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(6), s_green=>sig_aff_green(6), s_blue=>sig_aff_blue(6));
 
                i8 : trans port map(e_trans=>e_7seg, s_trans=>seg_trans);
 
                Sseg_red<= sig_aff_red(0) or sig_aff_red(1) or sig_aff_red(2) or sig_aff_red(3) or sig_aff_red(4) 
                                          or sig_aff_red(5) or sig_aff_red(6);
 
                Sseg_green<= sig_aff_green(0) or sig_aff_green(1) or sig_aff_green(2) or sig_aff_green(3) or sig_aff_green(4) 
                                          or sig_aff_green(5) or sig_aff_green(6);
 
                Sseg_blue<= sig_aff_blue(0) or sig_aff_blue(1) or sig_aff_blue(2) or sig_aff_blue(3) or sig_aff_blue(4) 
                                          or sig_aff_blue(5) or sig_aff_blue(6);
 
end a_aff;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- on a ajouté pixel_row et pixel column pour la suite
ENTITY VGA_SYNC IS
      PORT( clock_25Mhz        : IN   STD_LOGIC;
      horiz_sync_out, vert_sync_out   : OUT STD_LOGIC;
      pixel_row, pixel_column: OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END VGA_SYNC;
ARCHITECTURE aVGA_SYNC OF VGA_SYNC IS
      SIGNAL horiz_sync, vert_sync : STD_LOGIC;
      SIGNAL h_count, v_count :STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
 
-- Horiz_sync ------------------------------------__________--------
-- H_count      0             640           659       755 799
-- Bloc compteur du haut et gauche de la figure sur front montant
gestion_H_Count:PROCESS(clock_25Mhz) BEGIN
         IF(clock_25Mhz'EVENT) AND (clock_25Mhz='1') THEN
          IF (h_count = 799) THEN
           h_count <= (others =>'0');
          ELSE
           h_count <= h_count + 1;
          END IF;
     END IF;
END PROCESS;
gestion_Horiz_sync: PROCESS(clock_25Mhz,h_count) BEGIN
--Bloc comparateur du haut et à droite de la figure synchronisé sur front descendants
  IF(clock_25Mhz'EVENT) AND (clock_25Mhz='0') THEN
         IF (h_count <= 755) AND (h_count >= 659) THEN
                  horiz_sync <= '0';
         ELSE
                  horiz_sync <= '1';
         END IF;
  END IF;
END PROCESS;
-- Vert_sync     -----------------------------------------------_______------------
-- V_count        0                             480 493-494           524
-- Bloc compteur en bas à gauche de la figure
gestion_V_Count: PROCESS(clock_25Mhz,h_count) BEGIN
         IF(clock_25Mhz'EVENT) AND (clock_25Mhz='1') THEN
          IF (v_count >= 524) AND (h_count >= 699) THEN
                  v_count <= (others =>'0');
          ELSIF (h_count = 699) THEN
                  v_count <= v_count + 1;
          END IF;
         END IF;
END PROCESS;
gestion_Vertical_sync:PROCESS(clock_25Mhz,v_count) BEGIN
        IF(clock_25Mhz'EVENT) AND (clock_25Mhz='0') THEN
--Bloc comparateur du bas et à droite de la figure synchronisé sur front descendants
          IF (v_count <= 494) AND (v_count >= 493) THEN
                  vert_sync <= '0';
          ELSE
                  vert_sync <= '1';
          END IF;
        END IF;
END PROCESS;
 pixel_column <= h_count;
 pixel_row <= v_count;
 horiz_sync_out <= horiz_sync;
 vert_sync_out <= vert_sync;
END aVGA_SYNC;

library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;
-- afficheur complet sept segments
entity ligne8briques is
        generic (gx, gy, gdx, gdy : natural); --gx, gy = position ; gdx, gdy = tailles
        port(e_8 : in std_logic_vector(7 downto 0); -- valeur à affichier
          segx, segy : in std_logic_vector(9 downto 0);-- où en est le balayage de l'écran ?
          Sseg_red, Sseg_green, Sseg_blue : out std_logic); -- signaux de couleurs
end ligne8briques;
 
architecture a_ligne8briques of ligne8briques is
        component rect_generic
                generic(x,y,dx,dy : natural);
                port(vgax, vgay : in std_logic_vector(9 downto 0);
                  RGB : in std_logic_vector(2 downto 0);
                  e_rect : in std_logic;
                  s_red, s_blue, s_green : out std_logic);
        end component;
  
        signal sig_aff_red, sig_aff_green, sig_aff_blue : std_logic_vector(7 downto 0);
 
        begin
                i1 : rect_generic generic map (x=>gx+1, y=> gy+1, dx =>gdx-2, dy=>(gdy-gy)/8-2)
                  port map (RGB=>"100", e_rect=>e_8(0), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(0), s_green=>sig_aff_green(0), s_blue=>sig_aff_blue(0));
 
                i2 : rect_generic generic map (x=>gx+1, y=> gy+1+((gdy-gy)/8), dx =>gdx-2, dy=>(gdy-gy)/8-2)
                  port map (RGB=>"100", e_rect=>e_8(1), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(1), s_green=>sig_aff_green(1), s_blue=>sig_aff_blue(1));
 
                i3 : rect_generic generic map (x=>gx+1, y=> gy+1+(2*(gdy-gy)/8), dx =>gdx-2, dy=>(gdy-gy)/8-2)
                  port map (RGB=>"100", e_rect=>e_8(2), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(2), s_green=>sig_aff_green(2), s_blue=>sig_aff_blue(2));
 
                i4 : rect_generic generic map (x=>gx+1, y=> gy+1+(3*(gdy-gy)/8), dx =>gdx-2, dy=>(gdy-gy)/8-2)
                  port map (RGB=>"100", e_rect=>e_8(3), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(3), s_green=>sig_aff_green(3), s_blue=>sig_aff_blue(3));
 
                i5 : rect_generic generic map (x=>gx+1, y=> gy+1+(4*(gdy-gy)/8), dx =>gdx-2, dy=>(gdy-gy)/8-2)
                  port map (RGB=>"100", e_rect=>e_8(4), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(4), s_green=>sig_aff_green(4), s_blue=>sig_aff_blue(4));
 
                i6 : rect_generic generic map (x=>gx+1, y=> gy+1+(5*(gdy-gy)/8), dx =>gdx-2, dy=>(gdy-gy)/8-2)
                  port map (RGB=>"100", e_rect=>e_8(5), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(5), s_green=>sig_aff_green(5), s_blue=>sig_aff_blue(5));
 
                i7 : rect_generic generic map (x=>gx+1, y=> gy+1+(6*(gdy-gy)/8), dx =>gdx-2, dy=>(gdy-gy)/8-2)
                  port map (RGB=>"100", e_rect=>e_8(6), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(6), s_green=>sig_aff_green(6), s_blue=>sig_aff_blue(6));
 
                i8 : rect_generic generic map (x=>gx+1, y=> gy+1+(7*(gdy-gy)/8), dx =>gdx-2, dy=>(gdy-gy)/8-2)
                  port map (RGB=>"100", e_rect=>e_8(7), vgax=>segx, vgay=>segy, 
                        s_red=>sig_aff_red(7), s_green=>sig_aff_green(7), s_blue=>sig_aff_blue(7));
 
                Sseg_red<= sig_aff_red(0) or sig_aff_red(1) or sig_aff_red(2) or sig_aff_red(3) or sig_aff_red(4) 
                                          or sig_aff_red(5) or sig_aff_red(6) or sig_aff_red(7);
 
                Sseg_green<= sig_aff_green(0) or sig_aff_green(1) or sig_aff_green(2) or sig_aff_green(3) or sig_aff_green(4) 
                                          or sig_aff_green(5) or sig_aff_green(6) or sig_aff_green(7);
 
                Sseg_blue<= sig_aff_blue(0) or sig_aff_blue(1) or sig_aff_blue(2) or sig_aff_blue(3) or sig_aff_blue(4) 
                                          or sig_aff_blue(5) or sig_aff_blue(6) or sig_aff_blue(7);
 
end a_ligne8briques;

------------------------------------------------------------------------------
-- vgacassbrik.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          vgacassbrik.vhd
-- Version:           1.00.b
-- Description:       Top level design, instantiates library components and user logic.
-- Date:              Wed Dec 14 13:57:18 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;

library plbv46_slave_single_v1_00_a;
use plbv46_slave_single_v1_00_a.plbv46_slave_single;

library vgacassbrik_v1_00_b;
use vgacassbrik_v1_00_b.user_logic;

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_BASEADDR                   -- PLBv46 slave: base address
--   C_HIGHADDR                   -- PLBv46 slave: high address
--   C_SPLB_AWIDTH                -- PLBv46 slave: address bus width
--   C_SPLB_DWIDTH                -- PLBv46 slave: data bus width
--   C_SPLB_NUM_MASTERS           -- PLBv46 slave: Number of masters
--   C_SPLB_MID_WIDTH             -- PLBv46 slave: master ID bus width
--   C_SPLB_NATIVE_DWIDTH         -- PLBv46 slave: internal native data bus width
--   C_SPLB_P2P                   -- PLBv46 slave: point to point interconnect scheme
--   C_SPLB_SUPPORT_BURSTS        -- PLBv46 slave: support bursts
--   C_SPLB_SMALLEST_MASTER       -- PLBv46 slave: width of the smallest master
--   C_SPLB_CLK_PERIOD_PS         -- PLBv46 slave: bus clock in picoseconds
--   C_FAMILY                     -- Xilinx FPGA family
--
-- Definition of Ports:
--   SPLB_Clk                     -- PLB main bus clock
--   SPLB_Rst                     -- PLB main bus reset
--   PLB_ABus                     -- PLB address bus
--   PLB_UABus                    -- PLB upper address bus
--   PLB_PAValid                  -- PLB primary address valid indicator
--   PLB_SAValid                  -- PLB secondary address valid indicator
--   PLB_rdPrim                   -- PLB secondary to primary read request indicator
--   PLB_wrPrim                   -- PLB secondary to primary write request indicator
--   PLB_masterID                 -- PLB current master identifier
--   PLB_abort                    -- PLB abort request indicator
--   PLB_busLock                  -- PLB bus lock
--   PLB_RNW                      -- PLB read/not write
--   PLB_BE                       -- PLB byte enables
--   PLB_MSize                    -- PLB master data bus size
--   PLB_size                     -- PLB transfer size
--   PLB_type                     -- PLB transfer type
--   PLB_lockErr                  -- PLB lock error indicator
--   PLB_wrDBus                   -- PLB write data bus
--   PLB_wrBurst                  -- PLB burst write transfer indicator
--   PLB_rdBurst                  -- PLB burst read transfer indicator
--   PLB_wrPendReq                -- PLB write pending bus request indicator
--   PLB_rdPendReq                -- PLB read pending bus request indicator
--   PLB_wrPendPri                -- PLB write pending request priority
--   PLB_rdPendPri                -- PLB read pending request priority
--   PLB_reqPri                   -- PLB current request priority
--   PLB_TAttribute               -- PLB transfer attribute
--   Sl_addrAck                   -- Slave address acknowledge
--   Sl_SSize                     -- Slave data bus size
--   Sl_wait                      -- Slave wait indicator
--   Sl_rearbitrate               -- Slave re-arbitrate bus indicator
--   Sl_wrDAck                    -- Slave write data acknowledge
--   Sl_wrComp                    -- Slave write transfer complete indicator
--   Sl_wrBTerm                   -- Slave terminate write burst transfer
--   Sl_rdDBus                    -- Slave read data bus
--   Sl_rdWdAddr                  -- Slave read word address
--   Sl_rdDAck                    -- Slave read data acknowledge
--   Sl_rdComp                    -- Slave read transfer complete indicator
--   Sl_rdBTerm                   -- Slave terminate read burst transfer
--   Sl_MBusy                     -- Slave busy indicator
--   Sl_MWrErr                    -- Slave write error indicator
--   Sl_MRdErr                    -- Slave read error indicator
--   Sl_MIRQ                      -- Slave interrupt indicator
------------------------------------------------------------------------------

entity vgacassbrik is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
    C_HIGHADDR                     : std_logic_vector     := X"00000000";
    C_SPLB_AWIDTH                  : integer              := 32;
    C_SPLB_DWIDTH                  : integer              := 128;
    C_SPLB_NUM_MASTERS             : integer              := 8;
    C_SPLB_MID_WIDTH               : integer              := 3;
    C_SPLB_NATIVE_DWIDTH           : integer              := 32;
    C_SPLB_P2P                     : integer              := 0;
    C_SPLB_SUPPORT_BURSTS          : integer              := 0;
    C_SPLB_SMALLEST_MASTER         : integer              := 32;
    C_SPLB_CLK_PERIOD_PS           : integer              := 10000;
    C_FAMILY                       : string               := "virtex5"
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
	 hsynch,vsynch,red,green,blue : out STD_LOGIC;
    -- ADD USER PORTS ABOVE THIS LINE ------------------   
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    SPLB_Clk                       : in  std_logic;
    SPLB_Rst                       : in  std_logic;
    PLB_ABus                       : in  std_logic_vector(0 to 31);
    PLB_UABus                      : in  std_logic_vector(0 to 31);
    PLB_PAValid                    : in  std_logic;
    PLB_SAValid                    : in  std_logic;
    PLB_rdPrim                     : in  std_logic;
    PLB_wrPrim                     : in  std_logic;
    PLB_masterID                   : in  std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
    PLB_abort                      : in  std_logic;
    PLB_busLock                    : in  std_logic;
    PLB_RNW                        : in  std_logic;
    PLB_BE                         : in  std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
    PLB_MSize                      : in  std_logic_vector(0 to 1);
    PLB_size                       : in  std_logic_vector(0 to 3);
    PLB_type                       : in  std_logic_vector(0 to 2);
    PLB_lockErr                    : in  std_logic;
    PLB_wrDBus                     : in  std_logic_vector(0 to C_SPLB_DWIDTH-1);
    PLB_wrBurst                    : in  std_logic;
    PLB_rdBurst                    : in  std_logic;
    PLB_wrPendReq                  : in  std_logic;
    PLB_rdPendReq                  : in  std_logic;
    PLB_wrPendPri                  : in  std_logic_vector(0 to 1);
    PLB_rdPendPri                  : in  std_logic_vector(0 to 1);
    PLB_reqPri                     : in  std_logic_vector(0 to 1);
    PLB_TAttribute                 : in  std_logic_vector(0 to 15);
    Sl_addrAck                     : out std_logic;
    Sl_SSize                       : out std_logic_vector(0 to 1);
    Sl_wait                        : out std_logic;
    Sl_rearbitrate                 : out std_logic;
    Sl_wrDAck                      : out std_logic;
    Sl_wrComp                      : out std_logic;
    Sl_wrBTerm                     : out std_logic;
    Sl_rdDBus                      : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
    Sl_rdWdAddr                    : out std_logic_vector(0 to 3);
    Sl_rdDAck                      : out std_logic;
    Sl_rdComp                      : out std_logic;
    Sl_rdBTerm                     : out std_logic;
    Sl_MBusy                       : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
    Sl_MWrErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
    Sl_MRdErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
    Sl_MIRQ                        : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

  attribute SIGIS : string;
  attribute SIGIS of SPLB_Clk      : signal is "CLK";
  attribute SIGIS of SPLB_Rst      : signal is "RST";

end entity vgacassbrik;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of vgacassbrik is

  ------------------------------------------
  -- Array of base/high address pairs for each address range
  ------------------------------------------
  constant ZERO_ADDR_PAD                  : std_logic_vector(0 to 31) := (others => '0');
  constant USER_SLV_BASEADDR              : std_logic_vector     := C_BASEADDR;
  constant USER_SLV_HIGHADDR              : std_logic_vector     := C_HIGHADDR;

  constant IPIF_ARD_ADDR_RANGE_ARRAY      : SLV64_ARRAY_TYPE     := 
    (
      ZERO_ADDR_PAD & USER_SLV_BASEADDR,  -- user logic slave space base address
      ZERO_ADDR_PAD & USER_SLV_HIGHADDR   -- user logic slave space high address
    );

  ------------------------------------------
  -- Array of desired number of chip enables for each address range
  ------------------------------------------
  constant USER_SLV_NUM_REG               : integer              := 4;
  constant USER_NUM_REG                   : integer              := USER_SLV_NUM_REG;

  constant IPIF_ARD_NUM_CE_ARRAY          : INTEGER_ARRAY_TYPE   := 
    (
      0  => pad_power2(USER_SLV_NUM_REG)  -- number of ce for user logic slave space
    );

  ------------------------------------------
  -- Ratio of bus clock to core clock (for use in dual clock systems)
  -- 1 = ratio is 1:1
  -- 2 = ratio is 2:1
  ------------------------------------------
  constant IPIF_BUS2CORE_CLK_RATIO        : integer              := 1;

  ------------------------------------------
  -- Width of the slave data bus (32 only)
  ------------------------------------------
  constant USER_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;

  constant IPIF_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;

  ------------------------------------------
  -- Index for CS/CE
  ------------------------------------------
  constant USER_SLV_CS_INDEX              : integer              := 0;
  constant USER_SLV_CE_INDEX              : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);

  constant USER_CE_INDEX                  : integer              := USER_SLV_CE_INDEX;

  ------------------------------------------
  -- IP Interconnect (IPIC) signal declarations
  ------------------------------------------
  signal ipif_Bus2IP_Clk                : std_logic;
  signal ipif_Bus2IP_Reset              : std_logic;
  signal ipif_IP2Bus_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
  signal ipif_IP2Bus_WrAck              : std_logic;
  signal ipif_IP2Bus_RdAck              : std_logic;
  signal ipif_IP2Bus_Error              : std_logic;
  signal ipif_Bus2IP_Addr               : std_logic_vector(0 to C_SPLB_AWIDTH-1);
  signal ipif_Bus2IP_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
  signal ipif_Bus2IP_RNW                : std_logic;
  signal ipif_Bus2IP_BE                 : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
  signal ipif_Bus2IP_CS                 : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
  signal ipif_Bus2IP_RdCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
  signal ipif_Bus2IP_WrCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
  signal user_Bus2IP_RdCE               : std_logic_vector(0 to USER_NUM_REG-1);
  signal user_Bus2IP_WrCE               : std_logic_vector(0 to USER_NUM_REG-1);
  signal user_IP2Bus_Data               : std_logic_vector(0 to USER_SLV_DWIDTH-1);
  signal user_IP2Bus_RdAck              : std_logic;
  signal user_IP2Bus_WrAck              : std_logic;
  signal user_IP2Bus_Error              : std_logic;

begin

  ------------------------------------------
  -- instantiate plbv46_slave_single
  ------------------------------------------
  PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single
    generic map
    (
      C_ARD_ADDR_RANGE_ARRAY         => IPIF_ARD_ADDR_RANGE_ARRAY,
      C_ARD_NUM_CE_ARRAY             => IPIF_ARD_NUM_CE_ARRAY,
      C_SPLB_P2P                     => C_SPLB_P2P,
      C_BUS2CORE_CLK_RATIO           => IPIF_BUS2CORE_CLK_RATIO,
      C_SPLB_MID_WIDTH               => C_SPLB_MID_WIDTH,
      C_SPLB_NUM_MASTERS             => C_SPLB_NUM_MASTERS,
      C_SPLB_AWIDTH                  => C_SPLB_AWIDTH,
      C_SPLB_DWIDTH                  => C_SPLB_DWIDTH,
      C_SIPIF_DWIDTH                 => IPIF_SLV_DWIDTH,
      C_FAMILY                       => C_FAMILY
    )
    port map
    (
      SPLB_Clk                       => SPLB_Clk,
      SPLB_Rst                       => SPLB_Rst,
      PLB_ABus                       => PLB_ABus,
      PLB_UABus                      => PLB_UABus,
      PLB_PAValid                    => PLB_PAValid,
      PLB_SAValid                    => PLB_SAValid,
      PLB_rdPrim                     => PLB_rdPrim,
      PLB_wrPrim                     => PLB_wrPrim,
      PLB_masterID                   => PLB_masterID,
      PLB_abort                      => PLB_abort,
      PLB_busLock                    => PLB_busLock,
      PLB_RNW                        => PLB_RNW,
      PLB_BE                         => PLB_BE,
      PLB_MSize                      => PLB_MSize,
      PLB_size                       => PLB_size,
      PLB_type                       => PLB_type,
      PLB_lockErr                    => PLB_lockErr,
      PLB_wrDBus                     => PLB_wrDBus,
      PLB_wrBurst                    => PLB_wrBurst,
      PLB_rdBurst                    => PLB_rdBurst,
      PLB_wrPendReq                  => PLB_wrPendReq,
      PLB_rdPendReq                  => PLB_rdPendReq,
      PLB_wrPendPri                  => PLB_wrPendPri,
      PLB_rdPendPri                  => PLB_rdPendPri,
      PLB_reqPri                     => PLB_reqPri,
      PLB_TAttribute                 => PLB_TAttribute,
      Sl_addrAck                     => Sl_addrAck,
      Sl_SSize                       => Sl_SSize,
      Sl_wait                        => Sl_wait,
      Sl_rearbitrate                 => Sl_rearbitrate,
      Sl_wrDAck                      => Sl_wrDAck,
      Sl_wrComp                      => Sl_wrComp,
      Sl_wrBTerm                     => Sl_wrBTerm,
      Sl_rdDBus                      => Sl_rdDBus,
      Sl_rdWdAddr                    => Sl_rdWdAddr,
      Sl_rdDAck                      => Sl_rdDAck,
      Sl_rdComp                      => Sl_rdComp,
      Sl_rdBTerm                     => Sl_rdBTerm,
      Sl_MBusy                       => Sl_MBusy,
      Sl_MWrErr                      => Sl_MWrErr,
      Sl_MRdErr                      => Sl_MRdErr,
      Sl_MIRQ                        => Sl_MIRQ,
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
      IP2Bus_Data                    => ipif_IP2Bus_Data,
      IP2Bus_WrAck                   => ipif_IP2Bus_WrAck,
      IP2Bus_RdAck                   => ipif_IP2Bus_RdAck,
      IP2Bus_Error                   => ipif_IP2Bus_Error,
      Bus2IP_Addr                    => ipif_Bus2IP_Addr,
      Bus2IP_Data                    => ipif_Bus2IP_Data,
      Bus2IP_RNW                     => ipif_Bus2IP_RNW,
      Bus2IP_BE                      => ipif_Bus2IP_BE,
      Bus2IP_CS                      => ipif_Bus2IP_CS,
      Bus2IP_RdCE                    => ipif_Bus2IP_RdCE,
      Bus2IP_WrCE                    => ipif_Bus2IP_WrCE
    );

  ------------------------------------------
  -- instantiate User Logic
  ------------------------------------------
  USER_LOGIC_I : entity vgacassbrik_v1_00_b.user_logic
    generic map
    (
      -- MAP USER GENERICS BELOW THIS LINE ---------------
      --USER generics mapped here
      -- MAP USER GENERICS ABOVE THIS LINE ---------------

      C_SLV_DWIDTH                   => USER_SLV_DWIDTH,
      C_NUM_REG                      => USER_NUM_REG
    )
    port map
    (
      -- MAP USER PORTS BELOW THIS LINE ------------------
      --USER ports mapped here
		hsynch => hsynch,
		vsynch => vsynch,
		red    => red,
		green  => green,
		blue   => blue,
      -- MAP USER PORTS ABOVE THIS LINE ------------------

      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
      Bus2IP_Data                    => ipif_Bus2IP_Data,
      Bus2IP_BE                      => ipif_Bus2IP_BE,
      Bus2IP_RdCE                    => user_Bus2IP_RdCE,
      Bus2IP_WrCE                    => user_Bus2IP_WrCE,
      IP2Bus_Data                    => user_IP2Bus_Data,
      IP2Bus_RdAck                   => user_IP2Bus_RdAck,
      IP2Bus_WrAck                   => user_IP2Bus_WrAck,
      IP2Bus_Error                   => user_IP2Bus_Error
    );

  ------------------------------------------
  -- connect internal signals
  ------------------------------------------
  ipif_IP2Bus_Data <= user_IP2Bus_Data;
  ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
  ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
  ipif_IP2Bus_Error <= user_IP2Bus_Error;

  user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
  user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);

end IMP;